The Garp architecture and C compiler
Callahan, T.J.; Hauser, J.R.; Wawrzynek, J.
Computer
Volume 33, Issue 4, Apr 2000 Page(s):62 - 69
Digital Object Identifier 10.1109/2.839323
Summary:Various projects and products have been built using off-the-shelf
field-programmable gate arrays (FPGAs) as computation accelerators for
specific tasks. Such systems typically connect one or more FPGAs to the
host computer via an I/O bus. Some have shown remarkable speedups,
albeit limited to specific application domains. Many factors limit the
general usefulness of such systems. Long reconfiguration times prevent
the acceleration of applications that spread their time over many
different tasks. Low-bandwidth paths for data transfer limit the
usefulness of such systems to tasks that have a high
computation-to-memory-bandwidth ratio. In addition, standard FPGA tools
require hardware design expertise which is beyond the knowledge of most
programmers. To help investigate the viability of connected FPGA
systems, the authors designed their own architecture called Garp and
experimented with running applications on it. They are also
investigating whether Garp's design enables automatic, fast, effective
compilation across a broad range of applications. They present their
results in this article
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