A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters
Uwe Meyer-Baese; Jiajia Chen; Chip Hong Chang; Dempster, A.G.
Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on
Volume , Issue , 4-7 Dec. 2006 Page(s):1555 - 1558
Digital Object Identifier   10.1109/APCCAS.2006.342540
Summary:The paper starts with an overview of distributed arithmetic (DA) and n-dimensional reduced adder graph (RAG-n) multiplierless filter design methods. Since DA designs are table-based and RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Benchmark FIR filters (Goodman and Carey, 1977) of length 11 to 63 are compiled. For a wide set of realistic design examples, it will be shown that pipelined RAG-n designs achieve on average a gain of 71% in area, equivalent performance in speed, and a 56% improvement in cost compared with DA-based designs

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