Reconfigurable Implementation of Wavelet Transform on an Fpga-Augmented NIOS Processor
Eugene Hyun; Mihai Sima; Michael Mcguire
Electrical and Computer Engineering, 2006. CCECE apos;06. Canadian Conference on
Volume , Issue , May 2006 Page(s):1052 - 1055
Digital Object Identifier 10.1109/CCECE.2006.277376
Summary:The wavelet transform is a very popular tool in engineering for signal analysis. With respect to image compression, the new JPEG 2000 image standard incorporates wavelet transforms in its algorithm. Due to the high demands for processing and transmission, the trade-off of obtaining a high computation speed comes by sacrificing or reducing design flexibility. To meet the flexibility requirement, the discrete wavelet transform is implemented on an FPGA-augmented Nios processor. In particular, the lifting scheme is given reconfigurable-hardware support. To incorporate the newly defined lifting unit into the core processor, custom instructions are defined. This way, an ASIP-Nios can be defined on the fly at the expenses of FPGA utilization and custom instructions. Performance of the proposed design highlights significant speed improvement over a pure software implementation
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