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IP testing - the future differentiator?

Eklow, B.
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
Volume 3, Issue , 16-20 Feb. 2004 Page(s): 6 - 7 Vol.3
Digital Object Identifier   10.1109/DATE.2004.1269189
Summary: Testing of processors and mixed signal IP require large number of functional vectors to assure high coverage. Built-in-test features helps to reduce the vector count and increase coverage. Building bit error rate test capability and jitter test capability into the SerDes logic reduce the requirement for very expensive equipment to test these parameters. Power requirements for testing is larger than power requirements for functional operation. Testing in an SoC environment requires careful planning on the part of the IP integrator and careful attention to DFT on the part of the IP provider.

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