This article describes a proposal for the physical coding sublayer (PCS) for the 40-Gb/s and 100-Gb/s Ethernet interfaces currently under standardization within IEEE 802.3. This proposal has been submitted for consideration to the IEEE 802.3 HSSG (High Speed Study Group), but at this writing, no final decision has been made. This article also introduces a novel inverse-multiplexing scheme based on virtual lanes, which allows the PCS to support a wide variety of optical interface technologies (ranging from parallel to serial) and to accommodate advances in electrical signaling technologies (allowing the PCS electrical interface to get narrower and faster over time). The proposed solution applies equally to both 40 Gb/s and 100 Gb/s, but for simplicity this article focuses on the PCS layer and the novel requirements of the 100-Gb/s Ethernet.

Standardization for the next generation of Ethernet started in July 2006, when the IEEE 802.3 agreed to form a Higher Speed Study Group (HSSG). The early focus of the group was on 100 Gb/s only as the next rate for Ethernet. However, a key finding by the HSSG was a divergence betwen the computing and networking industries in bandwidth requirements. As a result, the HSSG completed a project authorization request (PAR) in July 2007 that included two new data rates-40 Gb/s for server and storage applications and 100 Gb/s for aggregation and core networking applications.

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GARY NICHOLL is a senior technical lead in the Core Routing business unit at Cisco Systems Inc. in Ottawa, Canada. He is responsible for the definition and development of high-speed optical interfaces on Cisco's core routing and switching platforms. He also leads Cisco's efforts on the definition of 100-Gb/s Ethernet technology, and is an active member of the IEEE High Speed Study Group (HSSG). He has over 20 years of experience in data and telecom product development. He holds a B.S. in electrical engineering from the University of Manchester, United Kingdom.

MARK GUSTLIN is a principal engineer in Cisco Systems' Core Routing business unit. He is responsible for the definition and development of high-speed modular interfaces for various routers and is active in the HSSG. Gustlin has over 20 years of experience in data and telecom system development. He holds a B.S. in electrical engineering from San Jose State University, California.

ODED TRAININ is a system architect in Cisco Systems' Core Routing business unit. Responsible for the definition and development of Cisco Carrier Routing System (CRS) architecture, Trainin has 18 years of experience in system architecture and VLSI and ASIC design. He holds a B.S. in electrical engineering from Technion-Israel Institute of Technology, Haifa.